A macrocell is a circuit, such as an NAND circuit and an OR circuit, or a combination of such circuits, which can perform functions desired by a user. A term "through-current" as used herein is defined as follows. For example, in a circuit including a series combination of an N-type MOS transistor (hereinafter referred to as NMOS transistor) and a P-type MOS transistor (hereinafter referred to as PMOS transistor), when, for example, the PMOS transistor changes from a nonconductive state to a conductive state and the NMOS transistor changes from a conductive state to a nonconductive state, both transistors may become conductive for some time due to difference in threshold between the PMOS and NMOS transistors. Current which flows through these two conductive transistors is called "through-current". In MOS transistor macrocells, such MOS transistor series circuits are frequently used, which often causes through-current to flow.
Power consumption in semiconductor circuits comprising macrocells when they are operating is computed in order to estimate power consumption to avoid troubles in the semiconductor circuits, such as degradation of performance of the circuits. In such computation, it is necessary to first compute power consumption in each of macrocells. Power consumption in a macrocell includes power consumption due to through-current and power consumption due to charging and discharging of load capacitance of in the macrocell.
FIG. 1 is a block diagram of a prior art apparatus for computing power consumption in one macrocell. The computation is carried out based on the results of logic simulation on a semiconductor circuit including that macrocell. In FIG. 1, circuit information deriving means 1 identifies a macrocell which has operated from data 2 relating to input/output signal variations in the logic simulation, names of macrocells, and a net list 3 storing information relating to how that macrocell is connected to other macrocells, and then derives the load capacitance of that macrocell as circuit information from load capacitance data 4.
Fixed-value storage means 5 stores a fixed value for each macrocell representing power consumption Np due to through-current in that macrocell as determined by applying a suitable input waveform and providing predetermined output load capacitance to that macrocell.
Through-current power consumption p determining means 6 reads out power consumption Np caused by through-current in a macrocell specified by circuit information deriving means 1 from fixed-value storage means 5.
Load-capacitance power consumption Nc determining means 7 computes power consumption Nc caused by charging or discharging of the load capacitance of a macrocell specified by circuit information deriving means 1. That is, means 7 computes the power consumption Wc according to well-known expressions for power consumption caused by load capacitance.
Summing means 8 sums the power consumption c and the power consumption Wp.
The above-described apparatus is for computing power consumption in one macrocell, but usually it is also necessary to compute overall power consumption of the semiconductor circuit formed of such macrocells.
For that purpose, as shown in prior art FIG. 2, means 9 for identifying the macrocells which have operated identifies the names of the respective macrocells having input/output signal changes in logic simulation, based on information from logic simulation result storage means 10 and net list 3. Means 9 also derives the number of operation cycles per unit time.
The data is fed to means 12 for deriving therefrom power consumption W1, 2, . . . , Wn in respective macrocells, as in the power consumption computing apparatus of FIG. 1, to compute power consumed in each cycle of operation of the respective macrocells (including power consumption due to through-current and power consumption due to load capacitance). In this example, the identification of macrocells which have operated is performed by means 9.
The thus computed power consumptions in the respective ones of macrocells are summed in summing means 13 which sums power consumption W1, W2, . . . , Wn. From the number of times the respective macrocells which have been identified by means 9 as having operated, the power consumption per unit time of each macrocell is determined. For example, if a macrocell has operated three times in a unit time period, the power consumed by that macrocell in the unit time period is computed by multiplying the power consumed in one operating cycle by the number of operating cycles, three in this case. Power consumed in the unit time period in other macrocells which have been identified as having operated is computed. The power consumption is summed to produce overall power consumption in the entire semiconductor circuit.
In Japanese Unexamined Patent Publication No. HEI 2-171861 (JP-A-21 71 861), a system for computing power consumption in a CMOS gate array is disclosed. According to the teaching of this Japanese patent publication, power consumption is computed from data relating to variations in input/output signals to and from the respective macrocells of the circuit, data to load capacitance and so forth. The technique shown therein first computes an operating frequency of a macrocell of interest from the input/output signal variations and, then, uses it in computing the power consumption. When the macrocell is a NAND circuit, the power consumed by the macrocell is determined by the product of the output frequency, the load capacitance and the power consumption factor inherent to that NAND circuit. If the macrocell is a D-type flip-flop, the power consumed by the macrocell is the sum of the input signal frequency multiplied by the power consumption factor of the flip-flop and the output frequency multiplied by the load capacitance and the power consumption factor. Such computation is similar to the computation of power consumption due to load capacitance in unit time of one macrocell shown in FIG. 1 or 2. This prior art does not take power consumption caused by through-current into consideration.
Since power consumption caused by through-current is not taken into consideration in this prior art technique, power consumption cannot be computed precisely. In the systems shown in FIGS. 1 and 2, power consumption due to through-current is taken into consideration, but it is treated as a fixed value. Therefore it is impossible to compute power consumption precisely.
Actual through-current is dependent on the slope of an input signal waveform applied to a macrocell, and the shift of operating points of OS transistors of the macrocell caused by changes in charge and discharge current for an output side load capacitance of the macrocell, and, therefore, power consumption Wp due to through-current is not constant. (Hereinafter, the above-stated slope of input signal waveform is referred to as input slew rate or slew rate.)
TABLE 1 shows the result of simulation for power consumption caused by through-current in a macrocell, e.g. NAND circuit.
TABLE 1 ______________________________________ Slew Rate Load 1.0 2.0 3.0 4.0 5.0 ______________________________________ 0.2 2.05 3.14 4.42 5.78 7.18 0.4 2.02 2.96 4.11 5.38 6.70 0.6 2.00 2.82 3.89 5.07 6.33 ______________________________________
TABLE 1 shows the result of simulation performed on a NAND circuit 40 shown in FIG. 3. NAND circuit 40 comprises two PMOS transistors 41 and 42 having their drain-source conduction paths connected between a +5 V voltage supply terminal and an output node Y, and also two NMOS transistors 43 and 44 having their drain-source conduction paths connected in series between output node Y and a point of reference potential. The gates of PMOS transistor 41 and NMOS transistor 43 are connected to an input terminal A, and the gates of PMOS transistor 42 and NMOS transistor 44 are connected to an input terminal B. Computation of power consumption in this circuit has been made on the assumption that input terminal A is fixed to, for example, +5 V and voltage change from +5 V to 0 V is applied to input terminal B. More specifically, initially, both input terminals A and B are at +5 V and, accordingly, both of NMOS transistors 43 and 44 are conductive, whereas both of PMOS transistors 41 and 42 are nonconductive. Therefore the voltage at output node Y is 0 V. When the voltage at input terminal B starts changing from +5 V toward 0 V, there will appear a time period during which PMOS transistor 42 and NMOS transistors 43 and 44 are all conductive, because the threshold voltage at which PMOS transistors change from nonconductive to conductive states is higher than the threshold voltage at which NMOS transistors change from conductive to nonconductive states. After that time period, NMOS transistor 44 becomes nonconductive so that output node Y becomes +5 V. Current which flows through PMOS transistor 42 and NMOS transistors 43 and 44 during the time period when these transistors 42, 43 and 44 are all conductive is "through-current".
In TABLE 1, "Slew Rate" is an input slew rate expressed in terms of nanoseconds (ns), "Load" is an output load capacitance in pico-farads (pF), and the power consumption is .mu. W/MHz. In this example, the slew rate is a function of an input-side overall capacitance c1 at terminal B, which is determined by the gate capacitance of each of NMOS and PMOS transistors 44 and 42, capacitance provided by metal conductors for connecting input terminal B of NAND circuit 40 to a macrocell in the preceding stage, for example, a similarly arranged NAND circuit 40a, and drain capacitance of each of MOS transistors of NAND circuit 40a corresponding to PMOS transistor 42 and NMOS transistors 43 and 44. An output-side capacitance c2 is determined by drain capacitance of each of PMOS transistor 42 and NMOS transistors 43 and 44 of NAND circuit 40, capacitance of wires for connecting NAND circuit 40 to a succeeding macrocell, e.g. an NAND circuit 40b similar to NAND CIRCUIT 40, and, further, the gate capacitance of each of MOS transistors of NAND circuit 40b corresponding to PMOS transistor 42 and NMOS transistor 44 if output node Y is connected to input terminal B' (not shown) of NAND circuit 40b. The reason why load capacitance c2 and input-side overall capacitance c1 as represented by "Slew Rate" have various values as shown in TABLE 1 is that, because the positions of NAND circuits used as NAND circuits 40a and 40b relative to NAND circuit 40 are not fixed due to circuit design, the lengths of metallic wires are different accordingly.
From TABLE 1, it is seen that in response to changes in slew rate and output-side load capacitance, power consumption in NAND circuit 40 varies in a range of from 2.00 to 7.18 .mu.W/MHz. However, while the actual power consumption is variable as shown, the prior art uses one fixed value within this variation range, e.g. a "true" value of 4.11 for a slew rate of 3.0 and load capacitance of 0.4, in computing the power consumption of NAND circuit 40. It is apparent that the use of such a fixed value provides less precise computation of power consumption.
An object of the present invention is to provide a power consumption computing apparatus free of the above-described disadvantages, which can compute power consumption in a macrocell precisely.